The present invention relates to semiconductor memory devices in general, and more particularly to flash memory cells having select gates and fabrication methods thereof.
A flash memory device is an advanced type of non-volatile memory device which can be erased electrically at a high speed without being removed from the circuit board as well as which retains information stored in its memory cells even when no power is supplied. Continuous improvements in flash memory technology had been made with different cell structures, which include stacked gate cells, split gate cells, source side injection cells and other types of cells, as described in U.S. Pat. No. 5,455,792 issued Oct. 3, 1995 to Yong-Wan Yi.
The stacked gate cell has floating gate and control gate electrodes, which are sequentially stacked. One example of the stacked gate cells is a cell proposed by Mukherjee et al. in U.S. Pat. No. 4,698,787 issued Oct. 6, 1987. The Mukherjee cell is shown in FIG. 1. The cell is formed on a substrate 101 and employs channel hot electron injection for programming of the cell at a drain 104 side and the Fowler-Nordheim (F-N) tunneling for erasing at a source 102 side. This stacked gate cell has been prevalently adopted as a unit cell of a number of flash memory devices with an advantage of its small cell size. Other recent examples of the stacked gate cells are disclosed by H. Watanabe et al. in 1998 IEDM Technical Digest, p. 975 in an article entitled xe2x80x9cNovel 0.44 um2 Ti-salicide STI cell technology for high-density NOR flash memories and high performance embedded applicationxe2x80x9d and in a Korean Patent Laid-open Publication No.99-48775. 
However, the stacked gate cell has a major disadvantage referred to as an over-erase problem. The over-erase problem occurs in stacked gate cells when the floating gate 110 in FIG. 1 is overly discharged during the erase operation. The threshold voltages of over-erased cells are negative and such cells conduct current even when they are not selected by a read voltage applied to the control gate 112.
In order to solve the over-erase problem, two different types of cells have been introduced, including a two-transistor cell structure, disclosed by Perlegos in U.S. Pat. No. 4,558,344 issued Dec. 10, 1985, and a split gate cell disclosed by Samachisa et al. in U.S. Pat. No. 4,783,766 issued Nov. 8, 1988. Perlegos employs a select transistor. A select gate in the Periegos cell blocks the leakage current from an over-erased floating gate when the cell is not selected. Similarly, the split gate cell of Samachisa et al. solved the problem by introducing a select gate portion of a channel under a control gate. The select gate portion has the function of blocking the leakage current coming from the floating gate portion of channel under an over-erased floating gate, when the control gate is turned off.
The major drawback of a split gate cell is low programming efficiency. Split gate cells are programmed by the conventional channel hot electron injection method, which has a very low programming efficiency. Such low injection efficiency unnecessarily wastes power and prohibits faster programming.
In order to improve the efficiency of hot electron injection to the floating gate, the source side injection (SSI) cell has been introduced by Wu et al. as disclosed in U.S. Pat. No. 4,794,565 issued Dec. 27, 1988 and Mar et al. as disclosed in U.S. Pat. No. 5,280,446 issued Jan. 18, 1994. The SSI cell of disclosed by Wu is formed on a substrate 201 having a source 202 and a drain 204, as shown in FIG. 2. A select gate 206, often called a sidewall gate, is positioned at the source side of the conventional stacked gate structure in order to induce the hot electron injection from the source 202 to a floating gate 210 when a high voltage is applied to a control gate 212. It was reported that drastic improvements of program efficiency were realized, in hot electron injections of the source side injection cell on the order of 1,000 to 10,000 times more efficient, as compared to the conventional channel hot electron injection.
Meanwhile, a new non-volatile memory cell was introduced which has a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure to reduce program voltage. The MONOS cell includes a thin dielectric layer composed of a lower silicon oxide layer (a tunnel oxide layer), a silicon nitride layer, and an upper silicon oxide layer (a top oxide layer). The thin dielectric layer is interposed between a semiconductor substrate and a control gate. The MONOS cell has state of a logic xe2x80x9c0xe2x80x9d when electrons are trapped in the silicon nitride layer. The MONOS cell has the other stage of a logic xe2x80x9c1xe2x80x9d when electrons are not trapped in the silicon nitride layer. An example of a MONOS cell is described in U.S. Pat. No. 5,930,631 issued Jul. 27, 1999 to Chih-Hsien Wang et al. As shown in FIG. 3, the Wang cell has a source 402, a drain 404 and a channel therebetween in a substrate 401. A select gate 406 is formed on the substrate 401. An ONO (oxide/nitride/oxide) layer 420 is formed on the select gate 406 and the substrate 401. A control gate 408 is formed on the ONO layer 420. A lightly doped drain (LDD) structure is adapted to the drain for the purpose of reducing hot carriers near the drain junction. In the programming mode, hot carriers tunnel to the ONO layer 420 and are trapped in the nitride layer. In order to accomplish this, the control gate 408, the select gate 406 and the drain 404 are positively biased while the source 402 is ground. In the erase mode, carriers tunnel from the ONO layer 420 to the drain 404. In the erasure mode, the drain 404 is at a high voltage while the select gate 406 is off. The select gate 406 serves to conserve power because the device is erased without causing current to flow through the channel of the device.
It is an object of the present invention to provide a non-volatile memory device having a minimized cell size and low power consumption during a program operation.
Another object of the present invention is to provide a method for forming a non-volatile memory device having a minimized cell size and low power consumption during a program operation.
According to one aspect of the invention, a non-volatile memory device comprises a substrate, a charge storage region stacked on the substrate, a control gate stacked on the charge storage region and a gate mask stacked on the control gate. The gate mask has a spacer-shape.
According to another aspect of the invention, a non-volatile memory device comprises a substrate having a source and a drain. The substrate also has a channel between the source and the drain. A charge storage region is formed on the channel, and a control gate is formed on the charge storage region. A select gate is formed on the channel and between charge storage region and the drain. The charge storage region, the channel, the drain, the control gate and the select gate constitute a first unit cell.
According to another aspect of the invention, a method for forming a non-volatile memory device comprises forming a charge storage layer on a substrate and forming a control gate layer on the charge storage layer. A gate mask having a spacer-shape is formed on the control gate layer. The charge storage layer and the control gate layer are partially removed. During the removal process, the gate mask protects a portion of the charge storage layer and the control gate layer to form a control gate and a charge storage region.
In a preferred embodiment, a select gate is formed on the substrate and a sidewall of the charge storage region, and a conductive region is formed on the substrate adjacent another sidewall of the charge storage region. The charge storage region, the control gate, the gate mask and the select gate constitute a first unit cell. A second unit cell, symmetrical and opposite to the first unit cell, may share the conductive region with the first unit cell.
The first unit cell may comprise a LDD spacer on a sidewall of the select gate.
A drain may be formed in the substrate adjacent to the select gate and opposite to the conductive region, and a bit line electrode may be electrically connected to the drain. A source electrode may be provided on the conductive region, wherein the source electrode is electrically isolated from the control gate by a source-side spacer.
The select gate is preferably in the shape of a spacer, and the charge storage region may comprise a floating gate dielectric layer on the substrate, a floating gate on the floating gate dielectric layer and an inter poly dielectric layer on the floating gate. Alternatively, the charge storage region preferably comprises an ONO layer.